Develop and design microarchitecture for core clocking, reset, and power management IPs for next generation processors. Collaborate with architecture, design verification, and physical design teams to ensure the successful integration of IPs into the an overall processor design using cutting edge fabrication technology. Create detailed specifications and documentation for

Lead Engineer responsible for architecting, documenting, designing, developing, testing, debugging, verifying and/or validating firmware. Lead day to day firmware requirements gathering, architecture and development, cross functional collaboration and delivery of integrated firmware solutions. Support all platforms and programs with fimware responsible for multi tasking a

Contribute to the long term roadmap of the Cores Advanced Development team. Data gathering, analysis, and mining. Simulation setup, execution, and driving to conclusive results for making engineering evaluations and critical decisions. Can span the range from circuit simulation to high level system simulations. Prototype new designs and design methodologies. PREFERRED EXP

Designing, implementing, and testing FPGA STA capabilities, suitable for placement, optimization, routing and signoff timing Conducting research and development of novel STA algorithms and optimization of existing STA algorithms to deliver multi fold improvements in quality of results (QOR), runtime, and memory, while maintaining timing accuracy Evaluating and providing S

Responsibilities include managing all aspects of new product introduction both internally with all factory stakeholders and externally by interfacing directly with customers and sales teams worldwide. Develop a strategic vision for the FPGA tools and IP product direction and drive the same with internal stakeholders. It is also critically important that the candidate can

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified. Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases. Estimate the time required to write the new feature tests and any required changes to the test environment. Buil

Relationship Owner Drive the annual executive engagement calendar between organizations across all functions of HPE business. Define and implement Sell In, Sell Through, and Sales Out strategies and quality account plans that grow revenue base and market share for all AMD products. Engage HPE and AMD teams to drive collaboration across all lines of business. Own the key s

Understand and interpret product failure and parametric data from accelerated stress testing. Perform reliability modeling estimations across varying usage and operating life conditions; model product lifetime conditions. Develop deep working knowledge of AMD's database structures for storing product manufacturing and test data. Develop models for product stress condition

Develop & optimize software systems for deploying AI solutions on Ryzen AI PCs Optimize Ryzen AI system level performance for multiple concurrent current AI workloads (Vision, Generative AI, Speech) and AMD devices (CPU, GPU, NPU) Optimize AI applications for Ryzen AI acceleration Work with cross functional teams to optimize various parts of the SW stack AI Compiler, AI f

Define performance suite and best practices for measuring GPU accelerated workloads to assess scalability and efficiency of AI models and algorithms Benchmark and analyze AI workloads in single and large multi node configurations comparing against previous generations and our competitors Perform comprehensive performance analysis and report findings for the entire platfor

Develop & optimize software systems for deploying AI solutions on Ryzen AI PCs Optimize Ryzen AI system level performance for multiple concurrent current AI workloads (Vision, Generative AI, Speech) and AMD devices (CPU, GPU, NPU) Optimize AI applications for Ryzen AI acceleration Work with cross functional teams to optimize various parts of the SW stack AI Compiler, AI f

Improve the performance of current generation AFX system. Participate in the development of next generation AFX from concept to production. Define hardware design requirements and specifications based on project objectives and internal customer needs. Lead board design through all development stages from spec definition, through electrical schematics to implementation, br

10+ years of experience Strong programming in C/C++ in Linux operating environment, strong understanding of Linux kernel internals, strong code review skills. Strong expertise in system level architecture design, reliability engineering, and fault tolerance mechanisms, optimizing RAS architectures for complex computing systems, data centers, or mission critical applicatio

Manage a high performance team of engineers that work directly creating At Scale abilities in batch jobs, code updates/enhancements, as well drive an overall framework of automation. Knowledge in requirements for improvements to make Validation teams have push button options for fleet deployment. Clear / concise communication and driving teams. Ability to recruit and hire

Train and finetune LLMs/LMMs. Improve on the state of the art LLMs/LMMs.. Accelerate the training and inference speed of LLMs/LMMs. Research novel ML techniques and model architectures. Influence the direction of AMD AI platform. Publish your work at top tier venues. PREFERRED EXPERIENCE Experience in developing and debugging in Python. Experience in ML frameworks such as